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Complex Computer Construction
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Complex Computer Construction
Complex Computer Construction
用户5691用户56912024年6月20日修改
Pipelining Basis
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Stages of single cycle CPU
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IF: instruction fetch from memory (inst mem)
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ID: instruction decoding and register read (reg)
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EX: execute operation or calculate address (ALU)
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MEM: access data memory operand (data mem)
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WB: write result back to register (reg)
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Notice that EX and WB are only related to registers
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Performance issues
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Longest delay determines clock period
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e.g. The lw instruction in right
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Most blocks are idle most of the time
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Pipelining improves performance by increasing instruction throughput
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Executes multiple instructions in parallel
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Each instruction has the same latency
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Mind that:
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ALU/Logic: IF, ID, ALU, WB; no MEM needed
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Jump/Branch: IF, ID, ALU; both MEM, WB don't needed
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Load: all five stages needed, including ALU
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Store: IF, ID, ALU, MEM; no WB needed
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In pipelined CPU, each stage takes one clock cycle
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Whereas in single-cycle, each instruction takes one clock cycle,
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That in pipelined,
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All cycles of the same length
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Speedup is based on
so we should expect a high acceleration
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In this case: originally
, now
, 4x speedup
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Speedup due to increased throughput, latency (time for each instruction) does not decrease
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When not specially mentioned, we consider a 5-stages case
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RISC-V ISA is designed for pipelining
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All instructions are 32-bits long, easier to fetch and decode
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Fewer and regular instruction format
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Instruction set design affects complexity of pipeline implementation
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Hazards
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Can usually resolve hazards by stall (waiting, using NOP)
▪
e.g. For 0.05*n NOPs, that is, we need to use
instead
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Structure hazards
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That a required resource is busy, e.g. A unified memory being used simultaneously
▪
The mem conflict case cannot be solved using NOP, because NOP is also an instruction that needs to be taken from inst-mem
▪
In RISC-V, we use two separate memories to solve: inst-mem and d-mem
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However, we do not always need a stall, because sometimes an instruction may actually not access some memory part
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Data hazards
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When data is needed to execute, the instruction is not yet available
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Two types: register usage (related to reg), load-use (related to mem loading, esp. data-mem)